1. Field
Exemplary embodiments of the present invention relate to a semiconductor device and, more particularly, to a level shifting circuit for use in the semiconductor device.
2. Description of the Related Art
In a semiconductor device such as a semiconductor memory device, as power consumption is reduced, the level of a voltage supplied thereto is lowered. Accordingly, in order to supply a signal with a specific voltage level applied from the outside of a semiconductor memory device to an internal circuit of the semiconductor memory device as a boosting voltage (or a back bias voltage), a level shifting circuit is used to convert a low voltage level to a high voltage level (or convert a high voltage level to a low voltage level). That is, the level shifting circuit may be employed to interface various circuits using voltages with levels different from each other.
For example, while a word line driver of the semiconductor memory device uses a boosting voltage VPP higher than an external voltage VDD as a power supply voltage, a signal swing between the external voltage VDD and a ground voltage VSS may be applied to drive the word line driver. When a circuit using the external voltage VDD as a power supply voltage is coupled to a circuit using the boosting voltage VPP as the power supply voltage, the level shifting circuit may be used.
A generally used level shifting circuit has been disclosed in Korean Patent Application No. 10-2006-0076417, entitled as “level shifter of semiconductor memory apparatus,” Korean Patent Registration No. 10-0907017, entitled as “level circuit of semiconductor memory apparatus,” and the like. Korean Patent Application No. 10-2006-0076417 discloses a level shifter driven by a single power supply voltage. Korean Patent Registration No. 10-0907017 discloses a level shifting circuit in which a current control unit is provided between nodes for coupling a pull-up element to a pull-down element to control a pull-up current delivered to an internal node or an output node, thereby allowing the voltage level of the internal node or the output node to quickly fall and rise, and resulting in the achievement of a stable and fast operating speed. However, the conventional art does not propose a detailed technology capable of stably operating with a smaller power supply voltage, e.g., a voltage smaller than 1.5 V, without error.